Over the past twenty-five years or so, the primary challenge of VLSI (very large scale integration) has been the integration of an ever-increasing number of MOSFET devices with high yield and reliability. This was achieved mainly by scaling down MOSFET gate/channel length, reducing gate dielectric thickness and increasing channel doping concentration.
In conventional complementary metal oxide semiconductor (CMOS) processes, the source, drain and gate regions of the MOSFET are implanted, activated annealed and thereafter silicided so as to produce low resistance junction regions in the substrate and poly-gate lines with low-sheet resistance. For high performance 0.1 μm CMOS devices, the conventional process of siliciding the poly-gates results in the following problem: For poly-gates having a width of 0.25 μm or less, nucleation limited growth of the silicided polysilicon, i.e., TiSi, results in very high-sheet resistance which causes reduction in device performance.
In view of the drawback mentioned above concerning conventional CMOS processing of high-performance sub-0.1 μm CMOS devices, there is a continued need for developing a new and improved method which enables the fabrication of high-performance sub-0.1 μm CMOS devices without the devices having high-sheet resistance poly gates. A method is also needed which avoids poly depletion in the gate region which is adjacent to the gate dielectric.